MODULE 4 · Syllabus 4.1.3 (a) · level 1

Chapter 5: Integrated Circuits and Logic Gates

What an integrated circuit is and how its pins are numbered, digital logic levels (TTL and CMOS, positive and negative logic), the seven basic gates with their symbols, truth tables and Boolean expressions, ANSI and IEC symbols, and how gate logic appears in aircraft warning and interlock systems.

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🎯 What you'll learn
  • What an integrated circuit is: monolithic chips, advantages and limits, scales of integration
  • IC packages (DIP, SOIC, QFP, BGA) and pin numbering
  • Logic levels: TTL and CMOS thresholds, positive and negative logic
  • The basic gates — NOT, buffer, AND, OR, NAND, NOR, XOR, XNOR — with truth tables and Boolean expressions
  • Universal gates and De Morgan's theorem
  • ANSI distinctive-shape and IEC rectangular symbols
  • Logic in aircraft systems — a simplified gear warning
📖 The lesson

What an integrated circuit is

An integrated circuit (IC) is a complete circuit — anything from a few transistors to billions — formed together on a single small chip of silicon, the die. Transistors, diodes, resistors and small capacitors are made in and on the chip by repeated doping, oxidation and metal-deposition steps, and interconnected by metal tracks on its surface. Fine gold or aluminium bond wires join the die to the package's lead frame, and the whole thing is sealed in plastic or ceramic. Because everything is made in one piece, this is called a monolithic IC. Hybrid circuits mount several chips and printed resistors on a ceramic substrate.

Dual in-line package (top view) 1 14 2 13 3 12 4 11 5 10 6 9 7 8 7400 pin 1: notch / dot count anticlockwise from above Inside: one silicon chip transistors, diodes, resistors on the die gold bond wires to the lead frame Scales of integration SSI up to ≈ 10 gates single gates (7400) MSI ≈ 10–100 gates counters, decoders LSI ≈ 100–10 000 early processors, memory VLSI > 10 000 processors, FPGAs
Integrated circuits. A complete circuit — transistors, diodes, resistors and their connections — is formed on one chip of silicon, bonded to a lead frame and sealed in a package. On a DIP, pin 1 is marked by a notch or dot, and pins are counted anticlockwise viewed from above. The scale of integration describes how many gates the chip holds.
  • Advantages: tiny size and weight; very high reliability, because thousands of connections are made inside the chip instead of by solder joints; low power; low cost per function; high speed.
  • Limitations: little power-handling ability; inductors and large capacitors cannot be integrated; a faulty IC cannot be repaired, so the chip, card or LRU is replaced; and many are sensitive to static and heat.
  • Two big families: digital (logic) ICs, which handle signals that are either HIGH or LOW, and linear (analogue) ICs, which handle continuously varying signals — operational amplifiers, regulators, audio and sensor amplifiers (Chapter 6). Mixed-signal chips such as converters and timers do both.
  • Scale of integration (roughly): SSI up to about 10 gates, MSI about 10–100, LSI about 100–10 000, VLSI beyond that — modern processors hold billions of transistors.

Packages and pin numbering

  • DIP (dual in-line package): two rows of pins on a 2.54 mm (0.1 in) pitch, for through-hole mounting or a socket. Pin 1 is identified by a notch at one end or a dot beside it. Seen from above with the notch at the top, pins are numbered anticlockwise — down the left side from pin 1 and back up the right. On a 14-pin DIP, pin 14 is therefore opposite pin 1.
  • Surface-mount packages: SOIC (small-outline, gull-wing leads on two sides), PLCC (J-leads on four sides), QFP (quad flat pack, fine gull-wing leads on four sides) and BGA (ball grid array, solder balls under the body, so the joints cannot be seen and are checked by X-ray). The same rule applies: find the pin-1 mark, then count anticlockwise viewed from the top.
  • Socketed ICs must go back in the same way round, matching the notch to the socket's mark. Never insert or remove them with power on.

Logic levels

Digital circuits work with two states: 1 and 0, also called HIGH/LOW, TRUE/FALSE or ON/OFF. Each logic family defines a voltage band for each state, with a forbidden band between them.

  • TTL (transistor–transistor logic, the 74-series): a 5 V supply. An input below 0.8 V is LOW and above 2.0 V is HIGH; outputs are guaranteed below 0.4 V or above 2.4 V, leaving a noise margin.
  • CMOS (4000 series at 3–18 V, 74HC at 2–6 V and today's 3.3 V and 1.8 V parts): its thresholds are roughly 30% and 70% of the supply. It uses very little power. Unused CMOS inputs must be tied HIGH or LOW — a floating input picks up noise and can make the chip oscillate or overheat.
  • Positive logic: HIGH = 1 — the normal convention. Negative logic: LOW = 1. Signals that are "true when LOW" (active-low) are marked by a bubble on the gate or a bar over the signal name.
TTL (5 V) inputs LOW undefined HIGH outputs LOW — HIGH 0.8 V 2.0 V 0.4 V 2.4 V 0 V 5 V CMOS (4000 series at 5 V) inputs ≈ 30% / 70% of supply LOW undefined HIGH 1.5 V 3.5 V supply 3–18 V · never leave inputs floating Positive and negative logic signal level positive negative HIGH (+) 1 0 LOW (0 V) 0 1 Most systems use positive logic. Active-low signals are marked with a bubble, or a bar over the name
Logic levels. A gate does not need an exact voltage: anything in its LOW band counts as 0 and anything in its HIGH band as 1. TTL runs on 5 V and reads below 0.8 V as LOW and above 2.0 V as HIGH. CMOS thresholds sit at roughly 30% and 70% of its supply. In positive logic HIGH means 1; in negative logic LOW means 1.

Aircraft systems pass many simple on/off signals between boxes as discretes, typically 28 V/open or ground/open. Interface circuits inside each LRU convert them to the chip's own logic levels.

The basic gates

A logic gate produces an output that depends only on its present inputs. A truth table lists the output for every input combination — 2ⁿ rows for n inputs, so 4 rows for two inputs and 8 for three. Boolean algebra writes the functions as expressions.

NOT (inverter) A Y Y = A A Y 0 1 1 0 AND A B Y Y = A · B A B Y 0 0 0 0 1 0 1 0 0 1 1 1 OR A B Y Y = A + B A B Y 0 0 0 0 1 1 1 0 1 1 1 1 XOR (exclusive OR) A B Y Y = A ⊕ B A B Y 0 0 0 0 1 1 1 0 1 1 1 0 NAND A B Y Y = A · B A B Y 0 0 1 0 1 1 1 0 1 1 1 0 NOR A B Y Y = A + B A B Y 0 0 1 0 1 0 1 0 0 1 1 0 XNOR A B Y Y = A ⊕ B A B Y 0 0 1 0 1 0 1 0 0 1 1 1 Buffer A Y Y = A A Y 0 0 1 1 1 only if A is 0 1 only if all are 1 1 if any is 1 1 if inputs differ 0 only if all are 1 1 only if all are 0 1 if inputs are equal same as input, more drive
The basic gates. Each gate's truth table lists its output for every combination of inputs — 2ⁿ rows for n inputs. The small circle (bubble) on an output means inversion: NAND, NOR and XNOR are AND, OR and XOR followed by a NOT.
GateExpressionOutput is 1 when…
NOT (inverter)Y = Athe input is 0 — it always gives the opposite
BufferY = Athe input is 1 — same logic, but more drive current or isolation
ANDY = A·Ball inputs are 1
ORY = A + Bany input is 1
NANDY = A·Bnot all inputs are 1 — it is 0 only when all inputs are 1
NORY = A + Bno input is 1 — it is 1 only when all inputs are 0
XOR (exclusive OR)Y = A ⊕ Bthe inputs are different
XNOR (exclusive NOR)Y = A ⊕ Bthe inputs are the same — an equality (coincidence) detector
Universal gates and De Morgan

NAND and NOR are universal: any logic function can be built from NAND gates alone, or from NOR gates alone. Tie a NAND's inputs together and you have a NOT. De Morgan's theorem links the two families: A·B = A + B and A + B = A·B. So a NAND is an OR with inverted inputs, and a NOR is an AND with inverted inputs. It also means a gate's job depends on the logic convention: in negative logic, a positive-logic AND gate acts as an OR, and a NAND as a NOR.

ANSI and IEC symbols

Two symbol standards are in everyday use, and both appear in maintenance manuals and in exams. The ANSI/IEEE distinctive shapes are common in American documentation. The IEC 60617 rectangular symbols are common in European documentation; they write the function inside the box.

Function ANSI / distinctive shape IEC 60617 rectangular Output is 1 when… AND & all inputs are 1 OR ≥1 at least one input is 1 NOT 1 the input is 0 NAND & not all inputs are 1 NOR ≥1 no input is 1 XOR =1 exactly one input is 1 XNOR =1 both inputs are the same
Two symbol standards. The American distinctive-shape symbols and the IEC rectangular symbols mean exactly the same thing. IEC writes the function inside the box: & AND, ≥1 OR, =1 exclusive OR and 1 for a buffer or inverter, with a circle on the output for inversion. Expect to read both.

Logic in aircraft systems

Warning, interlock and indication systems are logic. Examples are the gear and take-off configuration warnings, air/ground (weight-on-wheels) logic, reverser deploy interlocks (on the ground and lever selected) and BITE. Older aircraft built them from discrete gate ICs and relays; modern aircraft do the same thing in software or programmable logic inside an LRU. The maintenance manual still documents it as a logic diagram drawn with gate symbols, and fault isolation means tracing which input is stopping the output.

A simplified landing-gear warning left gear down & locked nose gear down & locked right gear down & locked NAND: 1 unless ALL three are locked thrust levers at idle radio altitude below limit gear not locked AND GEAR warning horn / light 1 = condition true (positive logic) · real aircraft add flap and override inputs — see the AMM logic diagram
Gates in an aircraft system. A three-input NAND outputs 1 whenever any gear leg is not down and locked. An AND gate then sounds the warning only if that is true and the thrust levers are at idle and the aircraft is low. Maintenance manuals draw system logic exactly like this, even when a computer does the work in software.
  • Gates whose output depends only on the present inputs make up combinational logic. Circuits with memory — flip-flops, counters, registers — are sequential logic, covered with number systems and computers in Module 5.
  • Logic ICs, especially CMOS, are static sensitive (Chapter 7). Handle cards by their edges, use a wrist strap, and keep spares in their shielding bags.
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